1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having at least a metal gate, and more particularly, to a method of manufacturing a semiconductor device having a metal gate with a U-shape work function layer.
2. Description of the Prior Art
Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as the metal-oxide-semiconductor (MOS). However, with a trend toward scaling down the size of semiconductor devices, the conventional poly-silicon gate has faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices. Therefore, work function metals are used to replace the conventional poly-silicon gate to be the control electrode that are suitable for use as the high-K gate dielectric layer.
In a complementary metal-oxide semiconductor (CMOS) device, one of the dual work function metal gates is used in an NMOS device and the other one is alternatively used in a PMOS device. It is well-known that compatibility and process control for the dual metal gate are more complicated, meanwhile thickness and composition controls for materials used in the dual metal gate method are more precise. The conventional dual metal gate methods are categorized into gate first processes and gate last processes. In a conventional dual metal gate method applied with the gate first process, the annealing process for forming the source/drain ultra-shallow junction, and the silicide process are performed after forming the metal gate. In the conventional gate last process, a sacrificial gate or a replacement gate is provided and followed by performing processes used to construct a normal MOS transistor. Then, the sacrificial/replacement gate is removed to form a gate trench. Consequently, the gate trench is filled with metals according to the different electrical requirements.
Though the gate last process is able to avoid processes of high thermal budget and to provide more material choices for the high-k gate dielectric layer and the metal gate, the gate last process still faces integrity requirements for the complicated processes and reliability requirement for the layers filling in the gate trench.